EP2A40F1020C9 [INTEL]

The APEX II Programmable Logic Device Family is manufactured using a 0.15-µm all-layer copper-metal fabrication process. It features high-speed differential I/O support (True-LVDS, LVPECL, PCML, HyperTransport) and flexible LVDS channels. The devices offer high-density architecture with up to 5,250,000 system gates, up to 67,200 logic elements (LEs), and up to 1,146,880 RAM bits. They include enhanced embedded system blocks (ESBs) for memory functions (FIFO, Dual-Port+ RAM, CAM) and support for high-speed external memory interfaces (ZBT, QDR, DDR SRAM, SDR/DDR SDRAM). The devices also feature flexible clock management with PLLs, multi-voltage I/O support (1.5V, 1.8V, 2.5V, 3.3V), and are configured via SRAM with byte-wide synchronous configuration.