EPF6016BC256-2 [Altera]

The Altera FLEX 6000 programmable logic device (PLD) family provides a low-cost alternative to high-volume gate array designs. Based on the OptiFLEX architecture, it minimizes die size while maintaining high performance and routability. Devices feature reconfigurable SRAM elements for design flexibility, in-circuit reconfigurability, and 100% functional testing. The architecture includes register-rich LUT-based design, built-in low-skew clock distribution, and dedicated carry/cascade chains. System-level features include JTAG boundary-scan test, MultiVolt I/O interface, low power consumption, and hot-socketing support for 3.3-V devices. Software design support is provided by Altera's development system with various package options including TQFP, PQFP, and BGA packages.