EPM7064BTC48-3 [INTEL]

The MAX7000B family is a high-density, high-performance PLD family based on Altera's second-generation MAX architecture. It features 2.5-V CMOS EEPROM technology, offering 600 to 10,000 usable gates and pin-to-pin delays as fast as 3.5 ns. The devices support in-system programming (ISP) via JTAG and are pin-compatible with the 5.0-V MAX7000S and 3.3-V MAX7000A families. Key system-level features include MultiVolt I/O interface (2.5-V core, I/O compatible with 3.3V, 2.5V, 1.8V), programmable power-saving mode (50% power reduction), fast input setup times via dedicated paths, support for advanced I/O standards (SSTL-2, SSTL-3, GTL+), bus-hold, PCI compatibility, programmable slew-rate control, open-drain output, programmable security bit, boundary-scan test (IEEE 1149.1), hot-socketing operation, and programmable ground pins. Advanced architecture features include a continuous routing structure (PIA), configurable expander product terms (up to 32 per macrocell), programmable macrocell registers with independent controls, two global clocks, programmable power-up states, and 6 to 10 output enables. The devices are available in a wide range of packages including TQFP, PQFP, BGA, FineLine BGA, and PLCC. Software support includes Altera's MAX+PLUS II development system and interfaces to industry-standard EDA tools.