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EPM7512BBC256-5 - INTEL | Electronic Components

Name: EPM7512BBC256-5
Brand: INTEL
SKU: EPM7512BBC256-5
Availability: InStock

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EPM7512BBC256-5 is a INTEL CPLD - Complex Programmable Logic Devices with EPM7032B Logic Array Blocks: 2 and EPM7064B Logic Array Blocks: 4. Review the product details or submit an RFQ if you need confirmation before purchase.

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Part No:

EPM7512BBC256-5

CPLD - Complex Programmable Logic Devices

Manufacturer:

INTEL

Description:

MAX 7000B devices are high-density, high-performance devices based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX7000B devices operate with a 2.5-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 3.5 ns, and counter speeds up to 303.0 MHz.

Datasheet:

Stock Status:

Available for RFQ

Pricing:

Request Volume Pricing

Quote Response:

Within 24 Hours

Shipping:

In-stock parts ship in 1–2 business days

Specification

Type

Parameter

Supply Voltage

2.5V

EPM7032B FCNT

303.0MHz

EPM7032B Logic Array Blocks

EPM7032B Macrocells

EPM7032B Max User Io Pins

EPM7032B Package

44-Pin PLCC, 44-Pin TQFP, 48-Pin TQFP, 49-Pin 0.8-mm Ultra FineLine BGA

EPM7032B Speed Grades

-3, -5, -7

EPM7032B TCO1

2.4 ns

EPM7032B TFSU

1.0 ns

EPM7032B TPD

3.5 ns

EPM7032B TSU

2.1 ns

Products Detail

The MAX 7000B family is a high-density, high-performance programmable logic device family based on Altera’s second-generation MAX architecture. These devices are fabricated with advanced CMOS EEPROM technology, operating at 2.5 V and providing 600 to 10,000 usable gates. They offer in-system programmability (ISP) via JTAG, with pin-to-pin delays as fast as 3.5 ns and counter frequencies up to 303.0 MHz. The family features MultiVolt I/O interface, programmable power-saving mode, and support for advanced I/O standards. Devices are available in a wide range of packages including PLCC, TQFP, BGA, and FineLine BGA.

Key Features

High-performance 2.5-V CMOS EEPROM-based PLDs Pin-compatible with MAX7000S and MAX7000A 600 to 10,000 usable gates 3.5-ns pin-to-pin delays, 303.0MHz counter frequencies Advanced 2.5-V ISP via JTAG MultiVolt I/O interface (2.5-V core, 3.3/2.5/1.8-V I/O) Programmable power-saving mode Fast input setup times (1.0 ns) Support for SSTL-2, SSTL-3, GTL+ Bus-hold option PCI compatible Programmable security bit Built-in boundary-scan (IEEE 1149.1) Hot-socketing support Programmable ground pins Programmable interconnect array (PIA) Configurable expander product-terms (up to 32 per macrocell) Programmable macrocell registers Two global clocks Programmable power-up states 6 to 10 output enables Advanced packages (TQFP, PQFP, BGA, FineLine BGA, PLCC) Software support (MAX+PLUS II, Quartus)