PM4329-FEI [Microchip]

The PM4329 HDLIU-32 features 32 short-haul T1 or E1 LIUs in a single device. The HDLIU-32 delivers unprecedented 32-channel T1/E1/J1 port density and is optimized for multi-service provisioning platforms (MSPPs), add/drop multiplexers (ADMs), wireless infrastructure, multi-service switches and edge routers. Traditional solutions rely on interconnecting the various semiconductor components with clock and data signals. Using the traditional approach to address these higher port count requirements quickly becomes cost prohibitive and requires more complexity for equipment designers as chip pin count and power consumption increase. To address this problem, the HDLIU-32 device supports a low trace count, high-density, industry standard Scalable Bandwidth Interconnect (SBI) bus. In addition, for transport applications, the device supports a variant of this interface referred to as the Scalable Bandwidth Interconnect Transport (SBI TR) bus. This technology enables Microchip to offer the lowest cost T1/E1/J1 mapper/framer/LIU solution in the industry.

The HDLIU-32 has a 7-watt typical power dissipation, provides a -40 to +85c industrial temperature operating range and is packaged in a single 27mm x 27mm L2BGA package.

Applications
• Voice Gateway
• 84 T1 Lines / 63 E1 Lines
• Integrated SONET/SDH ADM

• Monolithic device that integrates 32 T1/J1/E1 shorthaul line interface circuits
• Software selectable between E1 and T1 mode, in groups of 16 links
• Links 1-16 and 17-32 can be configured for either T1 or E1 mode
• Meets or exceeds T1/J1 and E1 shorthaul network access specifications including ANSI T1.102, T1.403, T1.408, AT&T TR 62411, ITUT G.703, G.704 as well as ETSI 300- 011, CTR-4, CTR-12, and CTR-13
• Provides encoding and decoding of B8ZS, HDB3, and AMI line codes
• Provides per receiver, clock recovery, and line performance monitoring
• Provides transmit and receive jitter attenuation
• Provides support for redundancy
• Provides a digitally programmable Shorthaul pulse template per transmitter
• Provides a selectable, per channel independent de-jittered T1 or E1 recovered clock for system timing and redundancy
• Provides PRBS generators and detectors on each tributary for error testing at DS1 and E1 rates as recommended in ITU-T O.151
• Provides an 8-bit microprocessor bus interface for configuration, control, and status monitoring
• Provides line and digital loopback modes
• Supports programmable inband loopback codes
• Uses line rate system clock
• Provides an IEEE 1149.1 (JTAG) compliant test access port (TAP) and controller for boundary scan test
• Supports the following system interfaces:
• High-density SBI bus interface
• High-density, low latency, SBI TR bus interface